The present invention relates to an amplification type solid-state imaging device and to a method for achieving a low-noise amplification type solid-state imaging device with a small pixel size.
Conventionally, an amplification type solid-state imaging device, which has a pixel section that has an amplification function and a scanning circuit provided at the periphery of the pixel section and reads pixel data by the scanning circuit, has been proposed as the amplification type solid-state imaging device. In particular, an APS (Active Pixel Sensor) type image sensor constructed of CMOS (Complementary Metal Oxide Semiconductor) advantageous for the integration of the pixel construction with the peripheral drive circuit and the signal processing circuit is known.
In the APS type image sensor, a photoelectric conversion section, an amplification section, a pixel selection section and a reset section need to be normally formed in one pixel. Therefore, the APS type image sensor employs three to four MOS transistors besides the photoelectric conversion section that is normally constructed of a photodiode.
However, if three to four MOS transistors are necessary for one pixel, it becomes a restriction on the reduction in the pixel size. Accordingly, a method for reducing the transistor count per pixel is proposed (refer to JP H09-46596 A).
FIG. 7 shows a circuit diagram of the essential part of the amplification type solid-state imaging device in which the transistor count per pixel is reduced. The amplification type solid-state imaging device is constructed of a photodiode 101, a transfer transistor 102 for transferring a signal charge accumulated in the photodiode 101, a reset transistor 131, an amplification transistor 132 and a pixel select transistor 133. In this case, it is known that remarkable noise reduction can be achieved and a high-quality image can be obtained if the photodiode 101 is of a buried type and signal charge transfer from the photodiode 101 is made complete.
The operation of the amplification type solid-state imaging device shown in FIG. 7 is shown in the timing chart of FIG. 8.
As shown in FIG. 8, during a period T1, a drive pulse φR(m) applied to the gate of the common reset transistor 131 goes high level to turn on the reset transistor 131 and raise the potential under the gate. Therefore, charge migration to the drain side of the common reset transistor 131 is caused by a common signal charge storage portion 108, and the voltage of the signal charge storage portion 108 is reset to a power voltage VDD.
Next, during a period T2, the drive pulse φR(m) applied to the gate of the common reset transistor 131 goes low level to turn off the reset transistor 131. However, since a drive pulse φS(m) applied to the gate of the common pixel select transistor 133 is still at high level and the pixel select transistor 133 is in ON-state, the reset level is read to a signal line 135 via a common amplification transistor 132. At this time, the amplification transistor 132 and a constant current load transistor 134 constitute a source follower circuit.
Next, during a period T3, the drive pulse φS(m) applied to the gate of the common pixel select transistor 133 goes low level to turn off the pixel select transistor 133, and a drive pulse φT(m,1) applied to the gate of the transfer transistor 102 of the (m,1)-th row goes high level to enter the ON-state to raise the potential of the gate. Therefore, the signal charge accumulated in the photodiode 101 of the (m,1)-th row is transferred to the signal charge storage portion 108.
Next, during a period T4, the drive pulse φT(m,1) applied to the gate of the transfer transistor 102 of the (m,1)-th row goes low level to turn off the transfer transistor 102. However, the voltage at the time of signal charge transfer is maintained in the common signal charge storage portion 108, and the drive pulse φS(m) applied to the gate of the common pixel select transistor 133 goes high level to enter the ON-state. Therefore, the signal level of the (m,1)-th row is read to the signal line 135 via the common amplification transistor 132.
Then, after one horizontal scanning period (1H), a signal charge from the photodiode 101 of the (m,2)-th row is conducted to the common reset transistor 131, the amplification transistor 132 and the pixel select transistor 133 via the transfer transistor 102 of the (m,2)-th for the pixel of the (m,2)-th row, and operation similar to that of the periods T1 through T4 are carried out.
With regard to the construction and operation, 2.5 transistors/pixel result when one common portion per two pixels, and 1.75 transistors/pixel result when one common portion per four pixels. That is, the above transistor count per pixel can be reduced in these examples.
However, in the conventional amplification type solid-state imaging device, the following problems occur with respect to the construction and operation. That is, assuming that the capacitance of the common signal charge storage portion 108 is CFD, then a charge-to-voltage conversion efficiency η for converting a signal charge ΔQsig from the photodiode 101 into a voltage signal ΔVsig becomes:η=G·ΔVsig/ΔQsig=G/CFD where G is the gain of the source follower circuit constructed of the amplification transistor 132 and the constant current load transistor 134 and normally has a value slightly smaller than one (0.8 to 0.9). In order to increase η, the capacitance CFD must be reduced. The capacity CFD of the signal charge storage portion 108 is a sum total of the drain side junction capacitance of the transfer transistor 102 connected to the signal charge storage portion 108, the gate capacitance of the amplification transistor 132 and a junction capacitance to the substrate. Accordingly, there is a problem that the charge-to-voltage conversion efficiency η is reduced as the photodiodes and transfer transistors connected to the common signal charge storage portion are increased in number.